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Home->Product and Design->ASIC Design
| No. | CPU model | Production time | Design | Process | Main feature | Application platform |
|---|---|---|---|---|---|---|
| 1 | T02V10 | 2008 | ODM | TSMC0.35um | 100MHz8051 | M100/M600/K600/H600/K600+ |
| 2 | T03V10 | 2010 | ODM | TSMC90m | display coprocessor | K600 |
| 3 | TPS01 | 2010 | ODM | TSMC0.25um | analog front end | K600+/DCS100 |
| 4 | T03V11 | 2012 | ODM | TSMC90nm | display coprocessor | K600+(DGUS) |
| 5 | T2 | 2015 | ODM | TSMC90m | 200MHz8051+FPGA | DGUS+/DGUSII |
| 6 | TPS03 | 2016 | ODM | TSMC0.18um | analog front end | MT500/DGUSII |
| 7 | T5 | 2017 | DWIN | TSMC40nm | 600MHz dual-core 8051 | MT500/DGUSII/DCS500 |
| 8 | T03V12 | 2017 | DWIN | TSMC40nm | display coprocessor | DGUSII |
| 9 | TPS05 | 2018 | DWIN | TSMC0.18um | analog front end | DGUSII/DCS500 |
| 10 | T5L | 2019 | DWIN | T5L1(55nm)/T5L2(40nm) | 250MHz dual-core 8051 | DGUSII |
| 11 | T5L0 | 2020 | DWIN | TSMC40nm | 18-bit color low cost version | DGUSII |
| 12 | T5L3 | 2020 | DWIN | TSMC40nm | Adding VPU and DDR on the basis of T5L2 | Multimedia platform |
| 13 | M3 | 2021 | DWIN | TSMC40nm | 400MHz ARM Cortex M3 core | High performance analog signal processor |
| 14 | T5G | 2021 | DWIN | TSMC40nm | 300MHz 8051*2+DWIN RISC CPU | DGUSII (streaming media application) |
| 15 | G5 | 2023 | DWIN | TSMC40nm | 16-core 500MHz 8051+1GHz DWIN 64bit RISC CPU | DGUSIII/AI |
| 16 | K5 | 2023 | DWIN | TSMC16nm | 4-core 2.2GHzRRM+3D accelerated GPU | Linux/Andrioid |